1. Technical Field
The embodiments described herein generally relate to a semiconductor integrated circuit, and more particularly, to a clock receiver in the semiconductor integrated circuit and a method of controlling the same.
2. Related Art
Typically, a semiconductor integrated circuit such as a Synchronous Dynamic Random Access Memory (SDRAM) has improved its operation speed by using a clock. For this improved operational speed, the semiconductor integrated circuit includes a clock buffer and buffers the clock inputted through a pad. In addition, the semiconductor integrated circuit uses the clock that is internally generated by compensating a phase difference with respect to the external clock, using a Delay Locked Loop (DLL) circuit or a Phase Locked Loop (PLL) circuit. As a result, the semiconductor integrated circuit inputs the external clock to generate the clock for internal use of the semiconductor integrated circuit. Accordingly, this semiconductor integrated circuit having an input from the external clock includes a clock receiver to receive and buffer the external clock. Typically the conventional clock receiver is generally configured with two differential amplifiers that are coupled with each other, and buffers the external clock to generate the clock which has a swing width suitable for inside of the semiconductor integrated circuit.
The semiconductor integrated circuit can be placed in various operation environments. The trend is toward having semiconductor integrated circuits to be configured to operate in environments where a high frequency operation is performed. Accordingly, the clock receiver is also manufactured to have a configuration suitable for the high frequency operation environment Therefore, this clock receiver for suitable for the high frequency operation environment is configured to increase a bias current applied to the internal differential amplifier of the semiconductor integrated circuit.
However, there are times when the semiconductor integrated circuit configured for the high frequency operation environment is not always placed in the high frequency operation environment wherein the semiconductor integrated circuit is placed in either a low frequency operation environment as well as the high frequency operation environment. As a result, when the semiconductor integrated circuit configured for the high frequency operation environment is placed in the low frequency operation environment and having the clock receiver configured suitable for the high frequency operation environment, this configuration causes a large amount of current consumption, thereby decreasing power efficiency of the semiconductor integrated circuit.
Therefore, the conventional clock receiver in the semiconductor integrated circuit lacks adaptability to the operation environment, thereby causing loss of power.